The present invention relates to a method of forming an alignment mark structure using standard process steps for forming vertical gate transistors.
During a typical semiconductor fabrication process, there are often one or more process steps involving the use of a mask after an opaque material layer has been formed that covers the wafer. Because such masks typically must be aligned with previously formed features or structures on the wafer, there is a need for an alignment mark, feature, or structure that can still be referenced when such an opaque material layer covers the wafer. A planar alignment mark covered by the opaque material layer does not provide much use at this stage if it cannot be seen through the opaque material layer.
Also, non-planar alignment features or structures are sometimes not useful when covered by an opaque material layer. Depending on the resulting thickness of the opaque material layer and/or depending on the type of process used to form the opaque material layer, a step feature or a trench of an alignment mark structure may not have sufficient height or depth to remain visible after forming the opaque material layer.
Conventionally to address these problems, extra processing steps are needed for the sole purpose of forming an alignment mark structure of sufficient size that it will remain visible after forming an opaque material layer over the alignment mark structure. Generally, however, reducing the number of process steps is desirable because this often reduces processing time, reduces materials usage, reduces production costs, reduces alignment error permutations, improves wafer yield, and/or simplifies the overall fabrication process. Thus, it would be highly desirable to reduce or eliminate dedicated processing steps performed solely for the formation of an alignment mark structure.
The problems and needs outlined above are addressed by the present invention. In accordance with one aspect of the present invention, a method for forming an alignment mark structure using standard process steps for forming a vertical gate transistor is provided. The method comprises the following steps, the order of which may vary: (i) forming a deep trench stud in an alignment mark region concurrently with a formation of a vertical gate transistor electrode in a circuit region; (ii) etching the stud to reduce a top area of the stud and forming an isolation trench in the alignment mark region adjacent to the stud, both concurrently with a formation of an isolation trench adjacent to the vertical gate transistor electrode in the circuit region; (iii) filling the alignment mark isolation trench with an insulating material while filling the circuit region isolation trenches with the insulating material; and (iv) removing a portion of the insulating material from the alignment mark isolation trench to a level below the top of the stud so that an upper portion of the stud extends above the insulating material, concurrently with a removal of a portion of the insulating material from the circuit region isolation trenches.
The method may further comprise the steps of: (v) forming an etch stop layer over the alignment mark region, concurrently with a formation of the etch stop layer over at least part of the circuit region; and (vi) shielding the stud from being etched during a subsequent etch, and retaining the stud during the subsequent etch. The etch stop layer may comprise a support gate oxide layer for planar devices in a support area of the circuit region. The method may further comprise the step of: (vii) removing the etch stop layer from the alignment mark structure concurrently with a removal of at least part of the etch stop layer from the circuit region. Also, the method may further comprise the step of: (viii) after the removing etch stop layer step, removing another portion of the insulating material from the alignment mark isolation trench to another level further below the top of the stud, concurrently with a removal of another portion of insulating material from the circuit region, such that the stud extends further above the insulating material of the alignment mark isolation trench. The subsequent etch may be performed to remove at least a portion of a support polysilicon layer formed for building a gate electrode on a planar transistor device in a support area of the circuit region.
The method may further comprise the steps of: (v) forming an etch stop layer over the alignment mark region, concurrently with a formation of the etch stop layer over at least part of the circuit region; (vi) forming a layer of polysilicon over the alignment mark region, concurrently with a formation of the polysilicon layer over at least part of the circuit region; (vii) removing the polysilicon layer at the alignment mark region, concurrently with an etch of at least part of the polysilicon layer at the circuit region; (viii) shielding the stud from being etched and retaining the stud during the step of etching the polysilicon layer; (ix) forming a layer of top oxide over the alignment mark region, concurrently with a formation of the top oxide layer over at least part of the circuit region; and (x) removing the top oxide layer at the alignment mark region, concurrently with an etch of at least part of the top oxide layer at the circuit region, to a level below the top of the stud. The etch stop layer may comprise a nitride material.
The method may still further comprise the step of: (xi) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. The opaque material layer may comprise metal. The method may still further comprise the steps of: (xi) removing the etch stop layer from the alignment mark structure concurrently with an etch of the circuit region. The method may further comprise the step of: (xii) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. Or, the method may further comprise the steps of: (xii) removing another portion of the insulating material from the alignment mark isolation trench to another level further below the top of the stud, concurrently with an etch of the circuit region; and (xiii) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region.
The method may further comprise the steps of: (v) forming a first etch stop layer over the alignment mark region, concurrently with a formation of the first etch stop layer over at least part of the circuit region; (vi) forming a layer of top oxide over the alignment mark region, concurrently with a formation of the top oxide layer over at least part of the circuit region; (vii) removing the top oxide layer at the alignment mark region, concurrently with a removal of at least part of the top oxide layer at the circuit region; and (viii) shielding the structures under the first etch stop layer from being removed during the step of removing the top oxide layer. The method may still further comprise the step of: (ix) removing the first etch stop layer at the alignment mark region, concurrently with a removal of at least part of the first etch stop layer at the circuit region. The method may still further comprise the steps of: (x) forming a second etch stop layer over the alignment mark region, concurrently with a formation of the second etch stop layer over at least part of the circuit region; (xi) forming a layer of polysilicon over the alignment mark region, concurrently with a formation of the polysilicon layer over at least part of the circuit region; (xii) removing the polysilicon layer at the alignment mark region, concurrently with a removal of at least part of the polysilicon layer at the circuit region; and (xiii) shielding the structures under the second etch stop layer from being removed during the step of removing the polysilicon layer. The method may still further comprise the step of (xiv) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. Or the method may still further comprise the steps of: (xiv) removing the second etch stop layer at the alignment mark region, concurrently with a removal of at least part of the second etch stop layer at the circuit region; and (xv) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region.
The method may further comprise the steps of: (v) forming a layer of polysilicon over the alignment mark region, concurrently with a formation of the polysilicon layer over at least part of the circuit region; and (vi) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. Also, the method may further comprise the steps of: (v) forming a layer of top oxide over the alignment mark region, concurrently with a formation of the top oxide layer over at least part of the circuit region; and (vi) removing the top oxide layer at the alignment mark region, concurrently with a removal of at least part of the top oxide layer at the circuit region. The method may still further comprise the step of (vii) removing another portion of the insulating material from the alignment mark isolation trench to another level further below the top of the stud, concurrently with a removal of material from the circuit region, such that the stud extends further above the insulating material of the alignment mark isolation trench. Or the method may still further comprise the steps of: (vii) forming an etch stop layer over the alignment mark region, concurrently with a formation of the etch stop layer over at least part of the circuit region; (viii) forming a layer of polysilicon over the alignment mark region, concurrently with a formation of the polysilicon layer over at least part of the circuit region; (ix) removing the polysilicon layer at the alignment mark region, concurrently with a removal of at least part of the polysilicon layer at the circuit region; and (x) shielding the structures under the etch stop layer from being removed during the step of removing the polysilicon layer. The method may still further comprise the step of (xi) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. Or the method may still further comprise the steps of: (xi) removing the etch stop layer at the alignment mark region, concurrently with a removal of at least part of the etch stop layer at the circuit region; and (xii) forming an opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region. The alignment mark region may be located in a kerf region of a wafer, in the circuit region, and/or the alignment mark structure may be part of an electrical component being formed in the circuit region, for example.
In accordance with another aspect of the present invention, a method for forming an alignment mark structure using standard process steps for forming a vertical gate transistor is provided, which comprises the step of forming a deep trench stud that extends above an adjacent surface in an alignment mark region, concurrently with a formation of a vertical gate transistor electrode in a circuit region. The method may further comprise the step of removing a nitride layer adjacent the stud in the alignment mark region, concurrently with the removal of at least part of the nitride layer in the circuit region. The method may still further comprise the steps of: forming an oxide layer over the alignment mark region, concurrently with the formation of the oxide layer over at least part of the circuit region; and removing the oxide layer in the alignment mark region, concurrently with the removal of at least part of the oxide layer in the circuit region. The method may still further comprise the steps of: forming an etch stop layer over the alignment mark region, concurrently with the formation of the etch stop layer in the circuit region; forming a polysilicon layer over the alignment mark region, concurrently with the formation of the polysilicon layer over at least part of the circuit region; and removing the polysilicon layer in the alignment mark region, concurrently with the removal of at least part of the polysilicon layer in the circuit region.
In accordance with yet another aspect of the present invention, method for aligning a mask with prior formed structures in an active area of a circuit region when an alignment mark region is covered by an opaque material layer is provided, which comprises the steps of: (i) forming an alignment mark structure in the alignment mark region using standard process steps for forming a vertical gate transistor, the forming alignment mark structure step comprising the steps of: (a) forming a deep trench stud in an alignment mark region concurrently with a formation of a vertical gate transistor electrode in a circuit region, (b) etching the stud to reduce a top area of the stud and forming an isolation trench in the alignment mark region adjacent to the stud, both concurrently with a formation of an isolation trench adjacent to the vertical gate transistor electrode in the circuit region, (c) filling the alignment mark isolation trench with an insulating material while filling the circuit region isolation trenches with the insulating material, and (d) removing a portion of the insulating material from the alignment mark isolation trench to a level below the top of the stud so that an upper portion of the stud extends above the insulating material, concurrently with a removal of a portion of the insulating material from the circuit region; (ii) forming the opaque material layer over the alignment mark region, concurrently with a formation of the opaque material layer over at least part of the circuit region; (iii) viewing the alignment mark structure through the mask, wherein a step feature formed by the stud is still present after the opaque material layer covers the alignment mark structure; and (iv) aligning an alignment mark portion of the mask with the alignment mark structure.
In accordance with still another aspect of the present invention, an alignment mark structure for aligning a mask with prior formed features of in a circuit region when an opaque material layer covers the alignment mark structure is provided. The alignment mark structure comprises: an alignment mark region stud, an isolation trench, and a step feature. The alignment mark region stud extends from a deep trench filled with gate material located in an alignment mark region. The alignment mark region stud is formed concurrently with a formation of a circuit region stud for a vertical gate transistor in a circuit region and without requiring additional processing steps solely for the formation of the alignment mark region stud. The alignment mark region stud has a top area defined by an active area mask. The isolation trench is formed adjacent to the deep trench filled with gate material in the alignment mark region. The alignment mark region isolation trench is filled with insulating material. The alignment mark region isolation trench filled with the insulating material is formed concurrently with a formation of an isolation trench filled with the insulating material that is located adjacent to the vertical gate transistor in the circuit region, and without requiring additional processing steps solely for the formation of the alignment mark region isolation trench filled with the insulating material. The step feature is formed between the top of the insulating material in the alignment mark region isolation trench and the top of the alignment mark region stud. The height of the step feature is large enough that the step feature remains visible after the opaque material layer covers the alignment mark structure.